1. Field of the Invention
This invention relates generally to programmable fuse arrays, and particularly to schemes for correcting programming failures in such arrays.
2. Description of the Related Art
Memory devices are increasingly used in analog circuits to configure their behavior. Such circuits are arranged such that one or more of their operating parameters can be set via the application of a digital input word, the bits of which are stored in the memory device. Examples include setting the gain and/or offset of an amplifier, setting the cut-off frequency of a filter, calibrating an analog-to-digital converter (ADC) or digital-to-analog converter (DAC), or defining an input-to-output characteristic for a non-linear amplifier.
One common type of non-volatile memory device is a programmable fuse; a blown fuse represents, for example, a logic ‘1’, and an intact or unblown fuse represents a logic ‘0’. Such fuses are typically provided in an array, and arranged to be individually programmed by means of a programming procedure that typically requires that a specified programming current be passed through any fuse that is to be blown; no programming current is passed through a fuse that is to remain intact. A means is typically provided to determine whether the fuses in an array have been successfully programmed. A ‘programming failure’ occurs when the programming procedure required to blow a particular fuse was executed, but was unsuccessful.
A number of schemes have been developed for correcting a programming failure of this sort. For example, U.S. Patent Application Publication 2008/0104472 to Tang describes a scheme that can be used to correct fuse-programming failures, in which a predetermined algorithm is used to compute a set of redundancy bits from the data bits to be stored. The calculated redundancy bits and the data bits are programmed into fuses. When the data and redundancy bits are read back, the algorithm is applied to the read-back data to calculate a new set of redundancy bits, which are compared to the read-back set of redundancy bits. If the sets differ, a programming failure is assumed and correction is attempted.
This scheme has two primary drawbacks. First, since redundancy bits are calculated for all data bits, programming time is increased on all parts, regardless of whether they exhibit a programming failure. Second, the scheme does not allow programming of additional fuses after the calculated redundancy bits have been programmed.
U.S. Patent Application Publication US 2007/0226400 to Tsukazaki describes a method by which significant corrections to the contents of a one-time-programmable memory can be made. The method requires the storage of the data needed to modify the contents of the memory, as well as the storage of data identifying the area of the memory to be modified.